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| 26. Mapping applications to an FPFA tile [field programmable function array]
| | *[http://faculty.cs.tamu.edu/rabi/ Rabi N. Mahapatra's homepage], Texas A&M |
| Rosien, M.A.J.; Yuanqing Guo; Smit, G.J.M.; Krol, T.;
| | *[http://students.cse.tamu.edu/ykim/ Yoonjin Kim's homepage], Texas A&M |
| Design, Automation and Test in Europe Conference and Exhibition, 2003
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| 2003 Page(s):1124 - 1125
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| Digital Object Identifier 10.1109/DATE.2003.1253764
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| Summary: This paper introduces a transformational design method which can be used to map code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a control data flow graph (C.....
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| AbstractPlus | Full Text: PDF(268 KB) IEEE CNF
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| 27. A decade of reconfigurable computing: a visionary retrospective
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| Hartenstein, R.;
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| Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings
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| 13-16 March 2001 Page(s):642 - 649
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| Digital Object Identifier 10.1109/DATE.2001.915091
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| Summary: The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm t.....
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| AbstractPlus | Full Text: PDF(1060 KB) IEEE CNF
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| 28. KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array architectures
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| Hartenstein, R.; Herz, M.; Hoffmann, T.; Nageldinger, U.;
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| Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
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| 25-28 Jan. 2000 Page(s):163 - 168
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| Digital Object Identifier 10.1109/ASPDAC.2000.835089
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| Summary: This paper introduces a CAD environment for design-space exploration of coarse grain reconfigurable KressArray architectures and similar platforms, To find an optimal solution to a given application domain this KressArray Xplorer supports experimenti.....
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| AbstractPlus | Full Text: PDF(652 KB) IEEE CNF
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| 29. Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors
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| Taniguchi, I.; Jayapala, M.; Raghavan, P.; Catthoor, F.; Sakanushi, K.; Takeuchi, Y.; Imai, M.;
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| Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
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| 19-22 Jan. 2009 Page(s):449 - 454
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| Digital Object Identifier 10.1109/ASPDAC.2009.4796521
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| Summary: Systematic architecture exploration from vast solution space is a complex problem in embedded system design. It is very difficult to explore a best architecture fast and accurately because accurate evaluation usually consumes significant amount of ti.....
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| AbstractPlus | Full Text: PDF(373 KB) IEEE CNF
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| 30. Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study
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| Chase, J.; Nelson, B.; Bodily, J.; Zhaoyi Wei; Dah-Jye Lee;
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| Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on
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| 14-15 April 2008 Page(s):173 - 182
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| Digital Object Identifier 10.1109/FCCM.2008.24
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| Summary: FPGA devices have often found use as higher-performance alternatives to programmable processors for implementing a variety of computations. Applications successfully implemented on FPGAs have typically contained high levels of parallelism and have of.....
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| AbstractPlus | Full Text: PDF(298 KB) IEEE CNF
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| 31. Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
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| Davila, J.; de Torres, A.; Sanchez, J.M.; Sanchez-Elez, M.; Bagherzadeh, N.; Rivera, F.;
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| Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
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| Volume 2, 6-10 March 2006 Page(s):6 pp.
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| Digital Object Identifier 10.1109/DATE.2006.243748
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| Summary: In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computational and has an important restriction in execution time due to the req.....
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| AbstractPlus | Full Text: PDF(361 KB) IEEE CNF
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| 32. Design space exploration for low-power reconfigurable fabrics
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| Mehta, G.; Hoare, R.R.; Stander, J.; Jones, A.K.;
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| Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
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| 25-29 April 2006 Page(s):4 pp.
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| Digital Object Identifier 10.1109/IPDPS.2006.1639484
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| Summary: This paper presents a parameterizable, coarse grained, reconfigurable fabric model that attempts to maintain field programmable gate array (FPGA)-like programmability and computer aided design (CAD), with application specific integrated circuit (ASIC.....
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| AbstractPlus | Full Text: PDF(3274 KB) IEEE CNF
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| 33. A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation
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| Verma, R.; Akoglu, A.;
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| Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on
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| 14-18 April 2008 Page(s):1 - 8
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| Digital Object Identifier 10.1109/IPDPS.2008.4536528
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| Summary: This paper proposes a novel application-specific hybrid coarsegrained reconfigurable architecture with a flexible network on chip (NoC) mechanism. Architecture supports variable block size motion estimation (VBSME) with much less resources than ASIC .....
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| AbstractPlus | Full Text: PDF(578 KB) IEEE CNF
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| 34. Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme
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| Xydis, S.; Economakos, G.; Pekmestzi, K.;
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| Embedded Computer Systems: Architectures, Modeling and Simulation, 2007. IC-SAMOS 2007. International Conference on
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| 16-19 July 2007 Page(s):137 - 144
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| Digital Object Identifier 10.1109/ICSAMOS.2007.4285744
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| Summary: This paper presents a design technique for coarse grained reconfigurable cores targeting mostly DSP applications. The proposed technique inlines flexibility into custom carry-save-arithmetic (CSA) datapaths exploiting a stable and canonical interconn.....
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| AbstractPlus | Full Text: PDF(3890 KB) IEEE CNF
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| 35. A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template
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| Hatanaka, A.; Bagherzadeh, N.;
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| Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International
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| 26-30 March 2007 Page(s):1 - 8
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| Digital Object Identifier 10.1109/IPDPS.2007.370371
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| Summary: Coarse grain reconfigurable arrays (CGRAs) have been drawing attention due to its programmability and performance. Compilation onto CGRAs is still an open problem. Several groups have proposed algorithms that software pipeline loops onto CGRAs. In th.....
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| AbstractPlus | Full Text: PDF(322 KB) IEEE CNF
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| 36. Instruction-Set Extension for Cryptographic Applications on Reconfigurable Platform
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| Majzoub, S.; Diab, H.;
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| System-on-Chip for Real-Time Applications, The 6th International Workshop on
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| Dec. 2006 Page(s):173 - 178
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| Digital Object Identifier 10.1109/IWSOC.2006.348231
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| Summary: Recently, the area of reconfigurable computing has received considerable interest. Reconfigurable system is a specific name that is used for any machine that can be reconfigured during runtime to execute an algorithm as a hardware circuit. As a middl.....
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| AbstractPlus | Full Text: PDF(3559 KB) IEEE CNF
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| 37. Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor
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| Hasegawa, Y.; Abe, S.; Kurotaki, S.; Vu Manh Tuan; Katsura, N.; Nakamura, T.; Nishimura, T.; Amano, H.;
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| Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
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| 25-29 April 2006 Page(s):8 pp.
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| Digital Object Identifier 10.1109/IPDPS.2006.1639431
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| Summary: Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed.....
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| AbstractPlus | Full Text: PDF(144 KB) IEEE CNF
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| 38. Evaluation strategies for coarse grained reconfigurable architectures
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| Lange, H.; Schroder, H.;
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| Field Programmable Logic and Applications, 2005. International Conference on
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| 24-26 Aug. 2005 Page(s):586 - 589
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| Digital Object Identifier 10.1109/FPL.2005.1515791
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| Summary: The granularity of a reconfigurable architecture has a big impact on important properties such as output data rate, area and energy consumption. Fine-grained architectures such as SRAM-based FPGAs provide good flexibility and speed, but they suffer f.....
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| AbstractPlus | Full Text: PDF(157 KB) IEEE CNF
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| 39. Stream applications on the dynamically reconfigurable processor
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| Suzuki, M.; Hasegawa, Y.; Yamada, Y.; Kaneko, N.; Deguchi, K.; Amano, H.; Anjo, K.; Motomura, M.; Wakabayashi, K.; Toi, T.; Awashima, T.;
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| Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
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| 2004 Page(s):137 - 144
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| Digital Object Identifier 10.1109/FPT.2004.1393261
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| Summary: Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on on.....
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| AbstractPlus | Full Text: PDF(773 KB) IEEE CNF
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| 40. A framework for reconfigurable computing: task scheduling and context management
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| Maestre, R.; Kurdahi, F.J.; Fernandez, M.; Hermida, R.; Bagherzadeh, N.; Singh, H.;
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| Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
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| Volume 9, Issue 6, Dec. 2001 Page(s):858 - 873
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| Digital Object Identifier 10.1109/92.974899
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| Summary: Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the de.....
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| AbstractPlus | Full Text: PDF(387 KB) IEEE JNL
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| 41. Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms
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| Ma, F.; Knight, J.P.; Plett, C.;
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| Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
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| Volume 13, Issue 5, May 2005 Page(s):553 - 563
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| Digital Object Identifier 10.1109/TVLSI.2005.844286
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| Summary: One of the challenges of designing for coarse-grain reconfigurable arrays is the need for mature tools. This is especially important because of the heterogeneity of the larger, more predefined (and hence more specialized) array elements. This work de.....
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| AbstractPlus | Full Text: PDF(680 KB) IEEE JNL
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| 42. Dynamically Mapping N-Point IDCT on Coarse-Grained Reconfigurable Platform CTaiJi
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| Liguo Song;
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| Future Generation Communication and Networking Symposia, 2008. FGCNS '08. Second International Conference on
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| Volume 3, 13-15 Dec. 2008 Page(s):99 - 102
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| Digital Object Identifier 10.1109/FGCNS.2008.25
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| Summary: The area of reconfigurable computing platform is consolidating itself as a bridge between application specific integrated circuit 1(ASIC) and general-purpose processors. There are two types of reconfiguration(dynamic and static). Dynamic reconfigurat.....
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| AbstractPlus | Full Text: PDF(267 KB) IEEE CNF
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| 43. Finite Domain Constraints Based Delay Aware Placement Tool for FPOAs
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| Saraswat, R.; Eames, B.;
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| Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
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| 3-5 Dec. 2008 Page(s):145 - 150
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| Digital Object Identifier 10.1109/ReConFig.2008.50
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| Summary: FPOAs are reconfigurable devices similar to FPGAs but offer a much higher level of abstraction than the gate level. The main advantage of FPOAs is their deterministic on chip network, which guarantees that an application executes at the design freque.....
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| AbstractPlus | Full Text: PDF(650 KB) IEEE CNF
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| 44. Performance improvements using coarse-grain reconfigurable logic in embedded SOCs
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| Dimitroulakos, G.; Galanis, M.D.; Goutis, C.E.;
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| Field Programmable Logic and Applications, 2005. International Conference on
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| 24-26 Aug. 2005 Page(s):630 - 635
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| Digital Object Identifier 10.1109/FPL.2005.1515801
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| Summary: A hardware/software partitioning methodology for improving applications' performance in embedded single-chip systems is presented. Critical software parts are accelerated on hardware of a system comprised by an embedded processor and coarse-grain rec.....
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| AbstractPlus | Full Text: PDF(211 KB) IEEE CNF
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| 45. When reconfigurable architecture meets network-on-chip
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| Soares, R.; Silva, I.S.; Azevedo, A.;
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| Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on
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| 7-11 Sept. 2004 Page(s):216 - 221
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| Summary: This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and.....
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| AbstractPlus | Full Text: PDF(422 KB) IEEE CNF
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| 46. Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study
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| Mei, B.; Vernalde, S.; Verkest, D.; Lauwereins, R.;
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| Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
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| Volume 2, 16-20 Feb. 2004 Page(s):1224 - 1229 Vol.2
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| Digital Object Identifier 10.1109/DATE.2004.1269063
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| Summary: Coarse-grained reconfigurable architectures have seen growing importance recently. Design tools and methodology are essential to their success. Based on our previous work on modulo scheduling algorithms and a novel architecture with tightly coupled V.....
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| AbstractPlus | Full Text: PDF(287 KB) IEEE CNF
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| 47. X4CP32: a coarse grain general purpose reconfigurable microprocessor
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| Soares, R.; Azevedo, A.; Silva, I.S.;
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| Parallel and Distributed Processing Symposium, 2003. Proceedings. International
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| 22-26 April 2003 Page(s):8 pp.
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| Digital Object Identifier 10.1109/IPDPS.2003.1213315
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| Summary: The X4CP32 is a novel coarse RPU runtime-reconfigurable general purpose microprocessor. It consists of 3 programming levels, based on a hierarchical array of easily and quickly reconfigurable entities. It brings a new concept of runtime reconfigurati.....
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| AbstractPlus | Full Text: PDF(402 KB) IEEE CNF
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