Reconfigurable Computing: Difference between revisions

Revision as of 15:22, 14 January 2008

RC: reconfigurable computing HPRC: high performance reconfigurable computing RH: reconfigurable hardware

R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", [http://site.ebrary.com.ezproxy1.lib.asu.edu/lib/asulib/Doc?id=10051293 Programmable Digital Signal Processors (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.

-UMass, Amherst

R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: A Survey", Journal of VLSI Signal Processing, May/June 2001, pp. 7-27

-UMass, Amherst

Wenyin Fu, Katherine Compton, "A Simulation Platform for Reconfigurable Computing Research", Field Programmable Logic and Applications, 2006. FPL '06. International Conference on 28-30 Aug. 2006 Page(s):1 - 7

-UWisconsin, Madison

Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson, [http://www.ecs.umass.edu/ece/tessier/tvlsi-ava.pdf "A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder", IEEE Transactions on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488

-UMass, Amherst

Last printed: 5.1

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 *Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson, [http://www.ecs.umass.edu/ece/tessier/tvlsi-ava.pdf "A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder", IEEE Transactions on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488
 :-UMass, Amherst
+<code>Last printed: 5.1</code>