Reconfigurable Computing: Difference between revisions

From esoterum.org
Jump to navigationJump to search
New page: *[http://en.wikipedia.org/wiki/Reconfigurable_computing Reconfigurable Computing on Wikipedia]
 
 
(44 intermediate revisions by the same user not shown)
Line 1: Line 1:
:RC: Reconfigurable Computing
:HPRC: High Performance Reconfigurable Computing
:RH: Reconfigurable Hardware
:ASIP: Appication Specific Instruction set Processors
*[http://en.wikipedia.org/wiki/Reconfigurable_computing Reconfigurable Computing on Wikipedia]
*[http://en.wikipedia.org/wiki/Reconfigurable_computing Reconfigurable Computing on Wikipedia]
*[http://ces.univ-karlsruhe.de/~henkel/ Henkel Embedded Systems page at Karlsruhe]
*[http://ces.univ-karlsruhe.de/RISPP/Overview.htm Overview: RISPP: Rotating Instruction Set Processing Platform]
*[http://ces.univ-karlsruhe.de/RISPP/AtomMoleculeModel_Overview.htm Atom/Molecule Concept from RISPP: Rotating Instruction Set Processing Platform website]
*[http://www.site.uottawa.ca/~rabielmo/personal/rc.html List of reconfigurable architectures]
== People ==
*[http://xputers.informatik.uni-kl.de/papers/main.html Reiner Hartenstein, University of Kaiserslautern]
*Scott Hauck
*Jörg Henkel, University of Karlsruhe
== Architectures ==
*(5.12) Takashi Miyamori, Kunle Olukotun, [http://electric.ee.psu.ac.th/ee/ieice/1999/pdf/e82-d_2_389.pdf REMARC: Reconfigurable Multimedia Array Coprocessor], IEICE Feb. 1999
:-Stanford University
*(5.11) Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao, [http://www.ee.washington.edu/faculty/hauck/publications/Chimaera.pdf The Chimaera Reconfigurable Functional Unit], IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
:-Northwestern University
== Industry ==
*[http://www.fpgajournal.com/articles_2008/20080226_drc.htm "Reconfigurable Computing for Acceleration in HPC"] by Michael R. D’Amour, DRC Computer Corporation FPGA and Structured ASIC Journal, February 26, 2008
:-RPUs are capable of providing under 250ns read latencies—less than half the latency seen on PCIe peripherals and far better than the microseconds latency experienced on PCI-X.
=== MPPA: Massively Parallel Processor Arrays ===
*[http://www.macobserver.com/article/2008/01/08.12.shtml Ambric Unleashes Teraops Video Processor, Gets Adobe Endorsement] (Am2045)
:-H.264 port PCI card for XP and Mac OS X The Am2045 GT uses only 15 watts of power while delivering video processing throughput equivalent to four quad-core CPUs.
=== Reconfigurable/Extensible Cores ===
*[http://www.tensilica.com/products/xtensa_overview.htm Tensilica's Xtensa reconfigurable core]
*[http://www.tensilica.com/pdf/xtensa_7.pdf Xtensa 7 Configurable Processor Core, product brief]
*[http://www.tensilica.com/pdf/xtensa_processor_v3.pdf Xtensa Processor Developer's Toolkit, overview]
*By Dennis Moolenaar, [http://www.iapplianceweb.com/story/oeg20030513s0050.htm MPEG-4 is accelerated and footprint reduced by use of a configurable processor core], Tensilica, Inc., Santa Clara, Ca., iApplianceWeb (05/14/03, 12:03:02 AM EDT)
=== COTS Journal ===
*Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44
:-MPPA: Massively Parallel Processor Arrays
:-In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors.  Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory.  Point-to-point communication between processors is directly realized in a configurable interconnect.  Each processor runs a specific task with the guarantee that no other processor with affect its state.  Hundreds of processors enable a full application to be divided naturally into a number of functions, each of which maps into a seperate processor.
== Papers ==
=== Surveys ===
*(5.10) Reiner Hartenstein, [http://www.ics.uci.edu/~dutt/ics212-wq05/hartenstein-recongtut-date01.pdf A Decade of Reconfigurable Computing: a Visionary Retrospective] CS Dept. (Informatik), University of Kaiserslautern, Germany
:-http://www.fpl.uni-kl.de hartenst{{@}}rhrk.uni-kl.de
*(5.13) Katherine Compton, Scott Hauck, [http://portal.acm.org/ft_gateway.cfm?id=508353&type=pdf&coll=GUIDE&dl=GUIDE&CFID=28096035&CFTOKEN=34964945 Reconfigurable Computing: A Survey of Systems and Software], ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.
:-Northwestern University, University of Washington
=== General ===
*R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", [http://site.ebrary.com.ezproxy1.lib.asu.edu/lib/asulib/Doc?id=10051293 ''Programmable Digital Signal Processors''] (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.
:-UMass, Amherst
*R. Tessier and W. Burleson, [http://www.ecs.umass.edu/ece/tessier/jvsp00.pdf "Reconfigurable Computing and Digital Signal Processing: A Survey"], Journal of VLSI Signal Processing, May/June 2001, pp. 7-27
:-UMass, Amherst
*(5.1) Wenyin Fu, Katherine Compton, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/4095018/4100939/04100974.pdf?tp=&arnumber=4100974&isnumber=4100939 "A Simulation Platform for Reconfigurable Computing Research"], Field Programmable Logic and Applications, 2006. FPL '06. International Conference on 28-30 Aug. 2006 Page(s):1 - 7
:-UWisconsin, Madison
*(5.4) M. Vuletic, L. Pozzi, P. Ienne, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/9306/29574/01342483.pdf?tp=&arnumber=1342483&isnumber=29574 "Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing"], 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Page(s):339 - 351
:-Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory
*(5.3) Proshanta Saha, Tarek El-Ghazawi, [http://ieeexplore.ieee.org/iel5/4297231/4297232/04297274.pdf?arnumber=4297274 "Software/Hardware Co-Scheduling for Reconfigurable Computing Systems"], International Symposium on Field-Programmable Custom Computing Machines, 2007
:-George Washington University
:*(5.2) Proshanta Saha, Tarek El-Ghazawi, [http://ieeexplore.ieee.org/iel5/4231755/4231756/04231792.pdf?tp=&isnumber=&arnumber=4231792 "A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems"], 2007 IEEE
::-George Washington University
*(5.6) M.D. Galanis, G. Dimitroulakos, C.E. Goutis, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/10334/32897/01540365.pdf?tp=&arnumber=1540365&isnumber=32897 "Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware"], 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, 23-25 July 2005 Page(s):50 - 55
:-University of Patras, Greece
*(5.5) L.S. Indrusiak, F. Lubitz, R. Reis, M. Glesner, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/8443/26600/01253726.pdf?tp=&arnumber=1253726&isnumber=26600 "Ubiquitous access to reconfigurable hardware: application scenarios and implementation issues"] Design, Automation and Test in Europe Conference and Exhibition, 2003 Page(s):940 - 945
:-Instituto de Informática, UFRGS, Porto Alegre, Brazil
:-Microelectronic Systems Institute, TU Darmstadt, Darmstadt, Germany
*(5.7) C. Claus, J. Zeppenfeld, F. Muller, W. Stechele, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/4211748/4211749/04211847.pdf?tp=&arnumber=4211847&isnumber=4211749 "Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System"], Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
*(5.8) Lars Bauer, Muhammad Shafique, Jörg Henkel, [http://ces.univ-karlsruhe.de/~bauer/pdf/RISPP_WASP07.pdf "Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation"], 5th Workshop on Application Specific Processors (WASP'07), Salzburg, Austria, October 2007
:-Karlsruhe
*(5.9) Lars Bauer, Muhammad Shafique, Dirk Teufel, Jörg Henkel, [http://ces.univ-karlsruhe.de/~bauer/pdf/RISPP_SASO07.pdf "A Self-Adaptive Extensible Embedded Processor"], IEEE/ACM First International Conference on Self-Adaptive and Self-Organizing Systems (SASO'07)
:-Karlsruhe
=== Adaptive Algorithm for Hardware Reconfiguration ===
*Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson, [http://www.ecs.umass.edu/ece/tessier/tvlsi-ava.pdf "A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder"], IEEE Transactions on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488
:-UMass, Amherst
<code>Last printed: 5.13</code>

Latest revision as of 18:03, 24 July 2008

RC: Reconfigurable Computing
HPRC: High Performance Reconfigurable Computing
RH: Reconfigurable Hardware
ASIP: Appication Specific Instruction set Processors


People

Architectures

-Stanford University
-Northwestern University

Industry

-RPUs are capable of providing under 250ns read latencies—less than half the latency seen on PCIe peripherals and far better than the microseconds latency experienced on PCI-X.

MPPA: Massively Parallel Processor Arrays

-H.264 port PCI card for XP and Mac OS X The Am2045 GT uses only 15 watts of power while delivering video processing throughput equivalent to four quad-core CPUs.

Reconfigurable/Extensible Cores

COTS Journal

  • Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44
-MPPA: Massively Parallel Processor Arrays
-In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors. Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory. Point-to-point communication between processors is directly realized in a configurable interconnect. Each processor runs a specific task with the guarantee that no other processor with affect its state. Hundreds of processors enable a full application to be divided naturally into a number of functions, each of which maps into a seperate processor.

Papers

Surveys

-http://www.fpl.uni-kl.de hartenstrhrk.uni-kl.de
-Northwestern University, University of Washington

General

  • R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", Programmable Digital Signal Processors (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.
-UMass, Amherst
-UMass, Amherst
-UWisconsin, Madison
-Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory
-George Washington University
-George Washington University
-University of Patras, Greece
-Instituto de Informática, UFRGS, Porto Alegre, Brazil
-Microelectronic Systems Institute, TU Darmstadt, Darmstadt, Germany
-Karlsruhe
-Karlsruhe

Adaptive Algorithm for Hardware Reconfiguration

-UMass, Amherst


Last printed: 5.13

Retrieved from "https://www.esoterum.org/mw/index.php?title=Reconfigurable_Computing&oldid=1840"