CSE591 Low Power Architecture: Difference between revisions
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==29 Jan 07 Presentation I== | == 29 Jan 07 Presentation I == | ||
[http://www.esoterum.org/mw/images/0/04/Instruction-level-power-dissipation.pdf Instruction Level Power Dissipation in the Intel XScale Embedded Microprocessor] | [http://www.esoterum.org/mw/images/0/04/Instruction-level-power-dissipation.pdf Instruction Level Power Dissipation in the Intel XScale Embedded Microprocessor] | ||
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:*[http://tab.computer.org/tcca/NEWS/jan2001/irwin.pdf SimplePower "A cycle accurate energy simulator"] | :*[http://tab.computer.org/tcca/NEWS/jan2001/irwin.pdf SimplePower "A cycle accurate energy simulator"] | ||
==5 Feb 07 Project I Topic due== | == 5 Feb 07 Project I Topic due == | ||
==12 Feb 07 Project I due== | == 12 Feb 07 Project I due == | ||
*[http://www.intel.com/design/PentiumD/documentation.htm Pentium D specifications (65nm, up to 5GHz)] | *[http://www.intel.com/design/PentiumD/documentation.htm Pentium D specifications (65nm, up to 5GHz)] | ||
:-[http://www.intel.com/design/packtech/ch_04.pdf Thermal/Failure Rate relationships, Fig. 4-27] | :-[http://www.intel.com/design/packtech/ch_04.pdf Thermal/Failure Rate relationships, Fig. 4-27] | ||
===[[Simulation Software]]=== | === [[Simulation Software]] === | ||
== | == [[/Project II|Project II]] == | ||
*XScale project using <del>PXA250</del> 80200 already in Dr. Shrivastava's possession. | *XScale project using <del>PXA250</del> 80200 already in Dr. Shrivastava's possession. | ||
== 19 Feb 07 Presentation II == | |||
==19 Feb 07 Presentation II== | |||
*[http://www.public.asu.edu/~ashriva6/teaching/LPCA/Readings/05B-01.pdf Mitigating Amdahl’s Law Through EPI Throttling] | *[http://www.public.asu.edu/~ashriva6/teaching/LPCA/Readings/05B-01.pdf Mitigating Amdahl’s Law Through EPI Throttling] | ||
:-[http://www.public.asu.edu/~ashriva6/teaching/LPCA/Readings/isca03_1.pdf Energy Efficient Co-Adaptive Instruction Fetch and Issue (Throttling paper)] | :-[http://www.public.asu.edu/~ashriva6/teaching/LPCA/Readings/isca03_1.pdf Energy Efficient Co-Adaptive Instruction Fetch and Issue (Throttling paper)] | ||
:-[http://www.public.asu.edu/~ashriva6/teaching/LPCA/Readings/ | :-[http://www.public.asu.edu/~ashriva6/teaching/LPCA/Readings/islped01.pdf Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors (Throttling paper)] | ||
*[http://en.wikipedia.org/wiki/Amdahl's_Law Amdahl's Law (Wikipedia)] | *[http://en.wikipedia.org/wiki/Amdahl's_Law Amdahl's Law (Wikipedia)] | ||
*[http://www.intel.com/technology/magazine/research/power-efficiency-0206.htm Intel article on EPI throttling] | *[http://www.intel.com/technology/magazine/research/power-efficiency-0206.htm Intel article on EPI throttling] | ||
*[http://www.iccd-conference.org/proceedings/2004/22310236.pdf Best of Both Latency and Throughput (introduces EPI Throttling)] | |||
=== Vocabulary === | |||
[http://en.wikipedia.org/wiki/Wall_clock_time Wall clock time] | |||
== 5 March 07 Project I.2 == | |||
'''Considerations:''' | |||
*Existing power reduction schemes for LCDs and their applicability to Electrophoretic Displays (EPDs) | |||
::-Dynamic Backlight and Contrast Scaling | |||
*The advantages of bi-stability of EPD over constant refresh of LCD | |||
::-Possibility of redraw circuitry for bi-stable display which only addressed pixels which need to be updated | |||
*Relevance of the backlight in LCD in comparison with "front-light" in EPD | |||
::-Best-case/Worst-case for each display and in what circumstances are they opposed, in what circumstances are they matched | |||
*Power characterization of power consumption of the LCD vs. the EPD | |||
*Power Modeling for LCD and EPD | |||
::-Traditionally pixel switching has been ignored because it is insignificant compared to backlight and control circuitry, is the EPD a different case | |||
::-LCD switching power modeled as capacitors ([[Display Technology#Display Power|1.16, 1.5, 1.10]]) | |||
::-EPD switching power modeled as resistor ([[Display Technology#Electrophroetic Displays|1.12]]) | |||
Latest revision as of 16:54, 2 March 2007
29 Jan 07 Presentation I
Instruction Level Power Dissipation in the Intel XScale Embedded Microprocessor
Tools for power analysis of microprocessors at the microarchitectural level:
- This software is based on the SimpleScalar software
- Download Wattch
5 Feb 07 Project I Topic due
12 Feb 07 Project I due
Simulation Software
Project II
- XScale project using
PXA25080200 already in Dr. Shrivastava's possession.
19 Feb 07 Presentation II
- -Energy Efficient Co-Adaptive Instruction Fetch and Issue (Throttling paper)
- -Instruction Flow-Based Front-end Throttling for Power-Aware High-Performance Processors (Throttling paper)
- Amdahl's Law (Wikipedia)
- Intel article on EPI throttling
- Best of Both Latency and Throughput (introduces EPI Throttling)
Vocabulary
5 March 07 Project I.2
Considerations:
- Existing power reduction schemes for LCDs and their applicability to Electrophoretic Displays (EPDs)
- -Dynamic Backlight and Contrast Scaling
- The advantages of bi-stability of EPD over constant refresh of LCD
- -Possibility of redraw circuitry for bi-stable display which only addressed pixels which need to be updated
- Relevance of the backlight in LCD in comparison with "front-light" in EPD
- -Best-case/Worst-case for each display and in what circumstances are they opposed, in what circumstances are they matched
- Power characterization of power consumption of the LCD vs. the EPD
- Power Modeling for LCD and EPD
- -Traditionally pixel switching has been ignored because it is insignificant compared to backlight and control circuitry, is the EPD a different case
- -LCD switching power modeled as capacitors (1.16, 1.5, 1.10)
- -EPD switching power modeled as resistor (1.12)
