Reconfigurable Computing: Difference between revisions

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== People ==
== People ==
*[http://xputers.informatik.uni-kl.de/papers/main.html Reiner Hartenstein, University of Kaiserslautern]
*[http://xputers.informatik.uni-kl.de/papers/main.html Reiner Hartenstein, University of Kaiserslautern]
*Scott Hauck
*Jörg Henkel, University of Karlsruhe
== Architectures ==
*(5.12) Takashi Miyamori, Kunle Olukotun, [http://electric.ee.psu.ac.th/ee/ieice/1999/pdf/e82-d_2_389.pdf REMARC: Reconfigurable Multimedia Array Coprocessor], IEICE Feb. 1999
:-Stanford University
*(5.11) Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao, [http://www.ee.washington.edu/faculty/hauck/publications/Chimaera.pdf The Chimaera Reconfigurable Functional Unit], IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
:-Northwestern University


== Industry ==
== Industry ==
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*[http://www.macobserver.com/article/2008/01/08.12.shtml Ambric Unleashes Teraops Video Processor, Gets Adobe Endorsement] (Am2045)
*[http://www.macobserver.com/article/2008/01/08.12.shtml Ambric Unleashes Teraops Video Processor, Gets Adobe Endorsement] (Am2045)
:-H.264 port PCI card for XP and Mac OS X The Am2045 GT uses only 15 watts of power while delivering video processing throughput equivalent to four quad-core CPUs.  
:-H.264 port PCI card for XP and Mac OS X The Am2045 GT uses only 15 watts of power while delivering video processing throughput equivalent to four quad-core CPUs.  
=== Reconfigurable/Extensible Cores ===
*[http://www.tensilica.com/products/xtensa_overview.htm Tensilica's Xtensa reconfigurable core]
*[http://www.tensilica.com/pdf/xtensa_7.pdf Xtensa 7 Configurable Processor Core, product brief]
*[http://www.tensilica.com/pdf/xtensa_processor_v3.pdf Xtensa Processor Developer's Toolkit, overview]
*By Dennis Moolenaar, [http://www.iapplianceweb.com/story/oeg20030513s0050.htm MPEG-4 is accelerated and footprint reduced by use of a configurable processor core], Tensilica, Inc., Santa Clara, Ca., iApplianceWeb (05/14/03, 12:03:02 AM EDT)


=== COTS Journal ===
=== COTS Journal ===
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== Papers ==
== Papers ==
=== Surveys ===
=== Surveys ===
*Reiner Hartenstein, [http://www.ics.uci.edu/~dutt/ics212-wq05/hartenstein-recongtut-date01.pdf A Decade of Reconfigurable Computing: a Visionary Retrospective] CS Dept. (Informatik), University of Kaiserslautern, Germany
*(5.10) Reiner Hartenstein, [http://www.ics.uci.edu/~dutt/ics212-wq05/hartenstein-recongtut-date01.pdf A Decade of Reconfigurable Computing: a Visionary Retrospective] CS Dept. (Informatik), University of Kaiserslautern, Germany
:-http://www.fpl.uni-kl.de hartenst{{@}}rhrk.uni-kl.de
:-http://www.fpl.uni-kl.de hartenst{{@}}rhrk.uni-kl.de


*Katherine Compton, Scott Hauck, [http://portal.acm.org/ft_gateway.cfm?id=508353&type=pdf&coll=GUIDE&dl=GUIDE&CFID=28096035&CFTOKEN=34964945 Reconfigurable Computing: A Survey of Systems and Software], ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.
*(5.13) Katherine Compton, Scott Hauck, [http://portal.acm.org/ft_gateway.cfm?id=508353&type=pdf&coll=GUIDE&dl=GUIDE&CFID=28096035&CFTOKEN=34964945 Reconfigurable Computing: A Survey of Systems and Software], ACM Computing Surveys, Vol. 34, No. 2, June 2002, pp. 171–210.
:-Northwestern University, University of Washington
:-Northwestern University, University of Washington


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<code>Last printed: 5.9</code>
<code>Last printed: 5.13</code>

Latest revision as of 18:03, 24 July 2008

RC: Reconfigurable Computing
HPRC: High Performance Reconfigurable Computing
RH: Reconfigurable Hardware
ASIP: Appication Specific Instruction set Processors


People

Architectures

-Stanford University
-Northwestern University

Industry

-RPUs are capable of providing under 250ns read latencies—less than half the latency seen on PCIe peripherals and far better than the microseconds latency experienced on PCI-X.

MPPA: Massively Parallel Processor Arrays

-H.264 port PCI card for XP and Mac OS X The Am2045 GT uses only 15 watts of power while delivering video processing throughput equivalent to four quad-core CPUs.

Reconfigurable/Extensible Cores

COTS Journal

  • Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44
-MPPA: Massively Parallel Processor Arrays
-In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors. Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory. Point-to-point communication between processors is directly realized in a configurable interconnect. Each processor runs a specific task with the guarantee that no other processor with affect its state. Hundreds of processors enable a full application to be divided naturally into a number of functions, each of which maps into a seperate processor.

Papers

Surveys

-http://www.fpl.uni-kl.de hartenstrhrk.uni-kl.de
-Northwestern University, University of Washington

General

  • R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", Programmable Digital Signal Processors (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.
-UMass, Amherst
-UMass, Amherst
-UWisconsin, Madison
-Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory
-George Washington University
-George Washington University
-University of Patras, Greece
-Instituto de Informática, UFRGS, Porto Alegre, Brazil
-Microelectronic Systems Institute, TU Darmstadt, Darmstadt, Germany
-Karlsruhe
-Karlsruhe

Adaptive Algorithm for Hardware Reconfiguration

-UMass, Amherst


Last printed: 5.13

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