EEE525 VLSI Design: Difference between revisions
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== Project == | |||
*[http://www.nanohub.org/resource_files/2007/05/02700/2007.04.25-koh-nt501.pdf Metal Capacitance, 20fF/um ??] | |||
== Digital Design == | == Digital Design == | ||
*[http://books.google.com/books?id=xEYhxhs7fDgC&pg=PA107&lpg=PA107&dq=calculate+vih+vil&source=web&ots=6HN_n6MTrA&sig=LZ_ecT-5_2gJGAgYacpGCHQ-vTo&hl=en#PPA99,M1 ''Cmos Logic Circuit Design''] By John P. Uyemura (Google online) | *[http://books.google.com/books?id=xEYhxhs7fDgC&pg=PA107&lpg=PA107&dq=calculate+vih+vil&source=web&ots=6HN_n6MTrA&sig=LZ_ecT-5_2gJGAgYacpGCHQ-vTo&hl=en#PPA99,M1 ''Cmos Logic Circuit Design''] By John P. Uyemura (Google online) | ||
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*[http://www.eas.asu.edu/ets/services/services/server/unix/documents/vlsi10.pdf VLSI Readme], with Cadence instructions | *[http://www.eas.asu.edu/ets/services/services/server/unix/documents/vlsi10.pdf VLSI Readme], with Cadence instructions | ||
*> [http://www.esoterum.org/mw/images/7/70/Vlsi2.eas.asu.edu-readme.pdf vlsi2 Read-me file] | *> [http://www.esoterum.org/mw/images/7/70/Vlsi2.eas.asu.edu-readme.pdf vlsi2 Read-me file] | ||
=== Virtuoso === | |||
*[http://bwrc.eecs.berkeley.edu/Classes/Icdesign/ee141_f03/CadenceLabs/Lab2/VirtuosoTutorial.htm Layout tutorial from Berkeley] | |||
*To add labels and pin names etc., use the Res, Cap or Diode name layer. | |||
*[http://www.es.lth.se/home/jpr/myguide/Personal.html On the "cannot be found in the switched master of the instance" ERROR] | |||
=== Tutorials === | === Tutorials === | ||
Latest revision as of 05:13, 24 April 2008
Project
Digital Design
- Cmos Logic Circuit Design By John P. Uyemura (Google online)
- -3.1.1 (p.106) Thorough treatment of Inverter VTC, calculating VIL and VIH
Homework 2
- prob. 2. Tutorial problems with answers from MIT
- prob. 2. Voltage Transfer Characteristics from Berkeley
Homework 3
- parasitic probe?
- Tutorial from MIT, calculating avg/integral
More Cadence Tutorials
- Cadence Tools Tutorial from beginning to automatically generated counter layout
- Full-Custom Design with Cadence - Tutorial, Graz
Cadence
- Configuration path:
/usr/local/cadence2/NCSU
- vlsi2.eas.asu.edu information
- VLSI Readme, with Cadence instructions
- > vlsi2 Read-me file
Virtuoso
- Layout tutorial from Berkeley
- To add labels and pin names etc., use the Res, Cap or Diode name layer.
- On the "cannot be found in the switched master of the instance" ERROR
Tutorials
- >> Advanced calculator tutorial from MIT
- > Advanced tutorial from UCLA
- > UWaterloo Tutorial, thorough on parametric analysis with some pPar information
- > Tutorial at UPenn
- > Lab Tutorial at UPenn
- > Tutorial at WPI
- > Tutorial at USC, Ppar variable information
- > Cadence Manual at NMSU
- Tutorial, VLSI
- Tutorial on Virtuoso Schematic editor from OSU, layout with ALU
- Berkeley Virtuoso tutorial
- Cadence FAQ
- NCSU CDK User FAQ
- Circuit simulation using Spectre (UT Dallas)
- Unlocking files
- -At the shell prompt, type
clsAdminTool, you'll get a>prompt. - -Type
ale /afs/asu.edu/users/m/b/a/mbaker7/cadence/EE525(using the correct path to your library). You should get a list of existing locks in that library. - -There are two ways to release the lock in question:
- To release all the locks in the library, type
are /full/path/to/your/library/directory - To release the lock on a particular file, type
asre /full/path/to/the/locked/file
- To release all the locks in the library, type
- -Type
quitorexit.
Spectre
Design Rules
Spectre
- Model Libraries:
- /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dN.m
- /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dP.m
