Difference between revisions of "Reconfigurable Computing"
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| − | :RC: | + | :RC: Reconfigurable Computing |
| − | :HPRC: | + | :HPRC: High Performance Reconfigurable Computing |
| − | :RH: | + | :RH: Reconfigurable Hardware |
| + | :ASIP: Appication Specific Instruction set Processors | ||
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*Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44 | *Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44 | ||
:-MPPA: Massively Parallel Processor Arrays | :-MPPA: Massively Parallel Processor Arrays | ||
| − | :-In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors. Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory. Point-to-point communication between processors is | + | :-In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors. Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory. Point-to-point communication between processors is directly realized in a configurable interconnect. Each processor runs a specific task with the guarantee that no other processor with affect its state. Hundreds of processors enable a full application to be divided naturally into a number of functions, each of which maps into a seperate processor. |
== Papers == | == Papers == | ||
Revision as of 16:06, 13 May 2008
- RC: Reconfigurable Computing
- HPRC: High Performance Reconfigurable Computing
- RH: Reconfigurable Hardware
- ASIP: Appication Specific Instruction set Processors
- Reconfigurable Computing on Wikipedia
- Henkel Embedded Systems page at Karlsruhe
- Overview: RISPP: Rotating Instruction Set Processing Platform
- Atom/Molecule Concept from RISPP: Rotating Instruction Set Processing Platform website
Contents
MPPA: Massively Parallel Processor Arrays
- -H.264 port PCI card for XP and Mac OS X The Am2045 GT uses only 15 watts of power while delivering video processing throughput equivalent to four quad-core CPUs.
Industry
- "Reconfigurable Computing for Acceleration in HPC" by Michael R. D’Amour, DRC Computer Corporation FPGA and Structured ASIC Journal, February 26, 2008
- -RPUs are capable of providing under 250ns read latencies—less than half the latency seen on PCIe peripherals and far better than the microseconds latency experienced on PCI-X.
COTS Journal
- Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44
- -MPPA: Massively Parallel Processor Arrays
- -In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors. Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory. Point-to-point communication between processors is directly realized in a configurable interconnect. Each processor runs a specific task with the guarantee that no other processor with affect its state. Hundreds of processors enable a full application to be divided naturally into a number of functions, each of which maps into a seperate processor.
Papers
- R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", Programmable Digital Signal Processors (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.
- -UMass, Amherst
- R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: A Survey", Journal of VLSI Signal Processing, May/June 2001, pp. 7-27
- -UMass, Amherst
- (5.1) Wenyin Fu, Katherine Compton, "A Simulation Platform for Reconfigurable Computing Research", Field Programmable Logic and Applications, 2006. FPL '06. International Conference on 28-30 Aug. 2006 Page(s):1 - 7
- -UWisconsin, Madison
- (5.4) M. Vuletic, L. Pozzi, P. Ienne, "Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing", 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Page(s):339 - 351
- -Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory
- (5.3) Proshanta Saha, Tarek El-Ghazawi, "Software/Hardware Co-Scheduling for Reconfigurable Computing Systems", International Symposium on Field-Programmable Custom Computing Machines, 2007
- -George Washington University
- (5.2) Proshanta Saha, Tarek El-Ghazawi, "A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems", 2007 IEEE
- -George Washington University
- (5.6) M.D. Galanis, G. Dimitroulakos, C.E. Goutis, "Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware", 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, 23-25 July 2005 Page(s):50 - 55
- -University of Patras, Greece
- (5.5) L.S. Indrusiak, F. Lubitz, R. Reis, M. Glesner, "Ubiquitous access to reconfigurable hardware: application scenarios and implementation issues" Design, Automation and Test in Europe Conference and Exhibition, 2003 Page(s):940 - 945
- -Instituto de Informática, UFRGS, Porto Alegre, Brazil
- -Microelectronic Systems Institute, TU Darmstadt, Darmstadt, Germany
- (5.7) C. Claus, J. Zeppenfeld, F. Muller, W. Stechele, "Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System", Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
- (5.8) Lars Bauer, Muhammad Shafique, Jörg Henkel, "Efficient Resource Utilization for an Extensible Processor through Dynamic Instruction Set Adaptation", 5th Workshop on Application Specific Processors (WASP'07), Salzburg, Austria, October 2007
- -Karlsruhe
- (5.9) Lars Bauer, Muhammad Shafique, Dirk Teufel, Jörg Henkel, "A Self-Adaptive Extensible Embedded Processor", IEEE/ACM First International Conference on Self-Adaptive and Self-Organizing Systems (SASO'07)
- -Karlsruhe
Adaptive Algorithm for Hardware Reconfiguration
- Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson, "A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder", IEEE Transactions on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488
- -UMass, Amherst
Last printed: 5.9
