Difference between revisions of "Reconfigurable Computing"

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*[http://www.fpgajournal.com/articles_2008/20080226_drc.htm "Reconfigurable Computing for Acceleration in HPC"] by Michael R. D’Amour, DRC Computer Corporation FPGA and Structured ASIC Journal, February 26, 2008
 
*[http://www.fpgajournal.com/articles_2008/20080226_drc.htm "Reconfigurable Computing for Acceleration in HPC"] by Michael R. D’Amour, DRC Computer Corporation FPGA and Structured ASIC Journal, February 26, 2008
 
:-RPUs are capable of providing under 250ns read latencies—less than half the latency seen on PCIe peripherals and far better than the microseconds latency experienced on PCI-X.
 
:-RPUs are capable of providing under 250ns read latencies—less than half the latency seen on PCIe peripherals and far better than the microseconds latency experienced on PCI-X.
 +
 +
=== COTS Journal ===
 +
*Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44
 +
:-MPPA: Massively Parallel Processor Arrays
 +
:-In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors.  Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory.  Point-to-point communication between processors is diredtly realized in a configurable interconnect.  Each processor runs oa specific task with the guarantee that no other processor with affect its state.  Hundreds of processors enable a full application to be divided naturally into a number of functions, each of which maps into a seperate processor.
  
 
== Papers ==
 
== Papers ==

Revision as of 17:16, 9 May 2008

RC: reconfigurable computing
HPRC: high performance reconfigurable computing
RH: reconfigurable hardware



Industry

-RPUs are capable of providing under 250ns read latencies—less than half the latency seen on PCIe peripherals and far better than the microseconds latency experienced on PCI-X.

COTS Journal

  • Paul Chen, "MPPA Strategy Puts DSP/FPGA Dominance in Check", COTS Journal, April 2008, p. 38-44
-MPPA: Massively Parallel Processor Arrays
-In contrast with multicore DSPs, which have a limited number of processors (8-12), MPPAs have hundreds of processors. Each processor in an MPPA is strictly encapsulated and accesses only its own code and memory. Point-to-point communication between processors is diredtly realized in a configurable interconnect. Each processor runs oa specific task with the guarantee that no other processor with affect its state. Hundreds of processors enable a full application to be divided naturally into a number of functions, each of which maps into a seperate processor.

Papers

  • R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", Programmable Digital Signal Processors (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.
-UMass, Amherst
-UMass, Amherst
-UWisconsin, Madison
-Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory
-George Washington University
-George Washington University
-University of Patras, Greece
-Instituto de Informática, UFRGS, Porto Alegre, Brazil
-Microelectronic Systems Institute, TU Darmstadt, Darmstadt, Germany
-Karlsruhe
-Karlsruhe


Adaptive Algorithm for Hardware Reconfiguration

-UMass, Amherst


Last printed: 5.9

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