Difference between revisions of "Reconfigurable Computing"
From esoterum.org
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:-(5.2) Proshanta Saha, Tarek El-Ghazawi, [http://ieeexplore.ieee.org/iel5/4231755/4231756/04231792.pdf?tp=&isnumber=&arnumber=4231792 "A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems"], 2007 IEEE | :-(5.2) Proshanta Saha, Tarek El-Ghazawi, [http://ieeexplore.ieee.org/iel5/4231755/4231756/04231792.pdf?tp=&isnumber=&arnumber=4231792 "A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems"], 2007 IEEE | ||
:-The George Washington University | :-The George Washington University | ||
| + | *M.D. Galanis, G. Dimitroulakos, C.E. Goutis, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/10334/32897/01540365.pdf?tp=&arnumber=1540365&isnumber=32897 "Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware"], 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, 23-25 July 2005 Page(s):50 - 55 | ||
| + | :-University of Patras, Greece | ||
| + | *L.S. Indrusiak, F. Lubitz, R. Reis, M. Glesner, [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/8443/26600/01253726.pdf?tp=&arnumber=1253726&isnumber=26600 "Ubiquitous access to reconfigurable hardware: application scenarios and implementation issues"] Design, Automation and Test in Europe Conference and Exhibition, 2003 Page(s):940 - 945 | ||
| + | :-Instituto de Informática, UFRGS, Porto Alegre, Brazil | ||
| + | :-Microelectronic Systems Institute, TU Darmstadt, Darmstadt, Germany | ||
| + | |||
=== Adaptive Algorithm for Hardware Reconfiguration === | === Adaptive Algorithm for Hardware Reconfiguration === | ||
Revision as of 12:57, 15 January 2008
RC: reconfigurable computing HPRC: high performance reconfigurable computing RH: reconfigurable hardware
Papers
- R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: Past, Present, and Future", Programmable Digital Signal Processors (online via ASU Library), Yu Wen Hu, ed., Marcel Dekker, New York, N.Y., 2002.
- -UMass, Amherst
- R. Tessier and W. Burleson, "Reconfigurable Computing and Digital Signal Processing: A Survey", Journal of VLSI Signal Processing, May/June 2001, pp. 7-27
- -UMass, Amherst
- (5.1) Wenyin Fu, Katherine Compton, "A Simulation Platform for Reconfigurable Computing Research", Field Programmable Logic and Applications, 2006. FPL '06. International Conference on 28-30 Aug. 2006 Page(s):1 - 7
- -UWisconsin, Madison
- (5.4) M. Vuletic, L. Pozzi, P. Ienne, "Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing", 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004. Page(s):339 - 351
- -Swiss Federal Institute of Technology Lausanne, Processor Architecture Laboratory
- (5.3) Proshanta Saha, Tarek El-Ghazawi, "Software/Hardware Co-Scheduling for Reconfigurable Computing Systems", International Symposium on Field-Programmable Custom Computing Machines, 2007
- -George Washington University
- -(5.2) Proshanta Saha, Tarek El-Ghazawi, "A Methodology for Automating Co-Scheduling for Reconfigurable Computing Systems", 2007 IEEE
- -The George Washington University
- M.D. Galanis, G. Dimitroulakos, C.E. Goutis, "Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware", 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, 23-25 July 2005 Page(s):50 - 55
- -University of Patras, Greece
- L.S. Indrusiak, F. Lubitz, R. Reis, M. Glesner, "Ubiquitous access to reconfigurable hardware: application scenarios and implementation issues" Design, Automation and Test in Europe Conference and Exhibition, 2003 Page(s):940 - 945
- -Instituto de Informática, UFRGS, Porto Alegre, Brazil
- -Microelectronic Systems Institute, TU Darmstadt, Darmstadt, Germany
Adaptive Algorithm for Hardware Reconfiguration
- Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson, "A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder", IEEE Transactions on VLSI Systems, vol. 13, no. 4, April 2005, pp. 484-488
- -UMass, Amherst
Last printed: 5.1
