Difference between revisions of "Low Power DSP"
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*[http://www.dsp-fpga.com/columns/Forward_Thinking/2006/03/ DSP chips take on many forms"], By Will Strauss, DSP-FPGA.com, March 18, 2006 | *[http://www.dsp-fpga.com/columns/Forward_Thinking/2006/03/ DSP chips take on many forms"], By Will Strauss, DSP-FPGA.com, March 18, 2006 | ||
*[http://bwrc.eecs.berkeley.edu/Presentations/Retreats/Winter_Retreat_Jan_2000/Posters/ppt/hayden_poster.ppt Reconfigurable Hardware Testbed for DSP] presentation for UC Berkeley | *[http://bwrc.eecs.berkeley.edu/Presentations/Retreats/Winter_Retreat_Jan_2000/Posters/ppt/hayden_poster.ppt Reconfigurable Hardware Testbed for DSP] presentation for UC Berkeley | ||
| + | *[http://www.dspdesignline.com/howto/198900164 Comment: Chip efficiency comes in many flavors"], By Jeff Bier, EE Times, 04/09/2007 | ||
Revision as of 19:02, 20 September 2007
- "Designing Low-Power Signal Processing Systems", By Mel Tsai, Inside DSP, June 1, 2004
- -"Integration Is Key: One key for designing a low-power embedded system is component integration. Not only does a low chip count and a small printed circuit board lead to lower cost and physically smaller devices, it can also help to dramatically reduce power consumption."
- DSP chips take on many forms", By Will Strauss, DSP-FPGA.com, March 18, 2006
- Reconfigurable Hardware Testbed for DSP presentation for UC Berkeley
- Comment: Chip efficiency comes in many flavors", By Jeff Bier, EE Times, 04/09/2007
