Difference between revisions of "EEE525 VLSI Design"

Revision as of 23:32, 15 March 2008

Digital Design

• Cmos Logic Circuit Design By John P. Uyemura (Google online)

-3.1.1 (p.106) Thorough treatment of Inverter VTC, calculating VIL and VIH

Homework 2

• prob. 2. Tutorial problems with answers from MIT
• prob. 2. Voltage Transfer Characteristics from Berkeley

Homework 3

• parasitic probe?
• Tutorial from MIT, calculating avg/integral

More Cadence Tutorials

• Cadence Tools Tutorial from beginning to automatically generated counter layout
• Full-Custom Design with Cadence - Tutorial, Graz

Cadence

• Cadence setup on Server

Configuration path: /usr/local/cadence2/NCSU

• vlsi2.eas.asu.edu information
• VLSI Readme, with Cadence instructions
• > vlsi2 Read-me file

Tutorials

• > Advanced tutorial from UCLA
• > UWaterloo Tutorial, thorough on parametric analysis with some pPar information
• > Tutorial at UPenn
• > Lab Tutorial at UPenn
• > Tutorial at WPI
• > Tutorial at USC, Ppar variable information
• > Cadence Manual at NMSU
• Tutorial, VLSI
• Tutorial on Virtuoso Schematic editor from OSU, layout with ALU
• Berkeley Virtuoso tutorial
• Cadence FAQ
• NCSU CDK User FAQ
• Circuit simulation using Spectre (UT Dallas)
• Unlocking files

-At the shell prompt, type clsAdminTool, you'll get a > prompt.

-Type ale /afs/asu.edu/users/m/b/a/mbaker7/cadence/EE525 (using the correct path to your library). You should get a list of existing locks in that library.

-There are two ways to release the lock in question:

To release all the locks in the library, type are /full/path/to/your/library/directory

To release the lock on a particular file, type asre /full/path/to/the/locked/file

-Type quit or exit.

Spectre

• Spectre documentation from UCI.edu

Design Rules

• Mosis design rules (SCN5M Deep)

Spectre

• Model Libraries: