Difference between revisions of "DVFS"
From esoterum.org
(→Switching Overhead) |
(→Switching Overhead) |
||
| Line 6: | Line 6: | ||
:-Xeon C-state transition times | :-Xeon C-state transition times | ||
:-P-state frequency example, (10 133MHz steps from 1.2GHz to 2.53Ghz) | :-P-state frequency example, (10 133MHz steps from 1.2GHz to 2.53Ghz) | ||
| − | :-"On dual-core Athlon X2 and Phenom I, it was for example impossible to use DVFS and get decent HD-video decoding. There are three important performance problems with dynamic power management: | + | :-"On dual-core Athlon X2 and Phenom I, it was '''for example impossible to use DVFS and get decent HD-video decoding.''' There are three important performance problems with dynamic power management: |
:Transitioning from one P-state to another takes a while, especially if you scale up. Active cores will probe idle or lower P-state cores quite frequently. The OS power manager has to predict whether or not the process will need more processing power soon or not. As a result the OS transitions a lot slower than the hardware." | :Transitioning from one P-state to another takes a while, especially if you scale up. Active cores will probe idle or lower P-state cores quite frequently. The OS power manager has to predict whether or not the process will need more processing power soon or not. As a result the OS transitions a lot slower than the hardware." | ||
Revision as of 16:19, 29 August 2010
DVFS, Wikipedia An article that need to be written.
Contents
Switching Overhead
- Johan De Gelas. Dynamic Power Management: A Quantitative Approach. Online: AnandTech.com. January 18, 2010.
- -Xeon C-state transition times
- -P-state frequency example, (10 133MHz steps from 1.2GHz to 2.53Ghz)
- -"On dual-core Athlon X2 and Phenom I, it was for example impossible to use DVFS and get decent HD-video decoding. There are three important performance problems with dynamic power management:
- Transitioning from one P-state to another takes a while, especially if you scale up. Active cores will probe idle or lower P-state cores quite frequently. The OS power manager has to predict whether or not the process will need more processing power soon or not. As a result the OS transitions a lot slower than the hardware."
- Intel Xeon Processor 5600 Series, Datasheet Volume I. March 2010.
- -p. 168: "Processor core (including shared cache) is unavailable for less than 2us during the frequency transition."
- Power consumption table for 5600 by C-state
- -p. 167: "Processor C-State Power Specifications" table power consumption by C-state
- Adrian Hoban. Designing Real-Time Solutions on Embedded Intel® Architecture Processors. Intel Corporation. May, 2010.
- Power consumption table for several processors at different power management C-states
- Taylor Kidd. There's got to be a catch. Intel Software Blog. April 29, 2008 at 9:24 am
- -20us transition overhead for all C-states?
- Advanced Configuration and Power Interface Specification. Hewlett-Packard, Intel, Microsoft, Toshiba Corporations, and Phoenix Technologies Ltd. Revision 4.0a. April 5, 2010
- Power Efficiency – Analysis and SW Development Recommendations for Intel® Atom™ based MID platforms. Intel Software Network. May 4, 2009 9:00 PM PDT.
- -Overview charts on C-State configuration details wakeup times and power consumption
- -Gives wakeup times, but don't know where they came from
- -example power performance by P-states
- Power states overview slides from University of Pittsburg, example of c-state selections over time
DVFS Project Resources
- Concise references for DVFS project from 2003 using speedstep on an IBM Thinkpad
- Good linux kernel reference
- Topic: Addressing the power cost of switching overhead in DVFS processors.
Experimental Setup
DVFS Papers
- Isci, Martonosi, Buyuktosunoglu, "Long-term Workload Phases: Duration Predictions and Applications to DVFS
- Prediction and switching overhead
- "The Simulation and Evaluation of Dynamic Voltage Scaling Algorithms", 1998
- "Intelligent Energy Manager (IEM) Benchmarking on a Freescale’s iMX31 Multimedia Processor", SEP 2006
- "Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors"
- M. Pedram, K. Choi, R. Soma, "Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Tradeoff Based on the Ratio of Off-Chip Access to On-Chip Computation Times"
- "DVFS information from the University of Colorado"
- Zhu, Mueller, "Feedback EDF Scheduling Exploiting Hardware-Assisted Asynchronous Dynamic Voltage Scaling, North Carolina State University"
