Difference between revisions of "Cell Broadband Engine"
From esoterum.org
| Line 3: | Line 3: | ||
== Articles == | == Articles == | ||
| − | '''[http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/search/searchresult.jsp?SortField=Score&SortOrder=desc&ResultCount=25&maxdoc=100&coll1=ieeejrns&coll2=ieejrns&coll3=ieeecnfs&coll4=ieecnfs&coll5=ieeestds&coll6=preprint&coll7=books&coll8=modules&srchres=0&isonlybook=yes&history=yes&queryText=%28cell+processor%3CIN%3Emetadata%29&oldqrytext=%28%28ibm+cell+processor%29%3Cin%3Emetadata%29&radiobutton=cit IEEE Search on Cell Processor]''' | + | *'''[http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/search/searchresult.jsp?SortField=Score&SortOrder=desc&ResultCount=25&maxdoc=100&coll1=ieeejrns&coll2=ieejrns&coll3=ieeecnfs&coll4=ieecnfs&coll5=ieeestds&coll6=preprint&coll7=books&coll8=modules&srchres=0&isonlybook=yes&history=yes&queryText=%28cell+processor%3CIN%3Emetadata%29&oldqrytext=%28%28ibm+cell+processor%29%3Cin%3Emetadata%29&radiobutton=cit IEEE Search on Cell Processor]''' |
| − | + | *'''[http://domino.research.ibm.com/comm/research_projects.nsf/pages/cellcompiler.refs.html External papers from the IBM web site]''' | |
*> (2.1) [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/4/33202/01564359.pdf?tp=&arnumber=1564359&isnumber=33202 D.C. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. Chaudhry, D. Cox, P. Harvey, P.M. Harvey, H.P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Pham, J. Pille, S. Posluszny, M. Riley, D.L. Stasiak, M. Suzuoki, O. Takahashi, J. Warnock, S. Weitzel, D. Wendel, K. Yazawa, ''Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor'', Technol. Group, IBM Syst., Austin, TX, USA, IEEE Journal of Solid-State Circuits, Volume: 41 , Issue: 1, pp. 179-196, Jan. 2006] | *> (2.1) [http://ieeexplore.ieee.org.ezproxy1.lib.asu.edu/iel5/4/33202/01564359.pdf?tp=&arnumber=1564359&isnumber=33202 D.C. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. Chaudhry, D. Cox, P. Harvey, P.M. Harvey, H.P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Pham, J. Pille, S. Posluszny, M. Riley, D.L. Stasiak, M. Suzuoki, O. Takahashi, J. Warnock, S. Weitzel, D. Wendel, K. Yazawa, ''Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor'', Technol. Group, IBM Syst., Austin, TX, USA, IEEE Journal of Solid-State Circuits, Volume: 41 , Issue: 1, pp. 179-196, Jan. 2006] | ||
Revision as of 18:09, 26 July 2007
IBM
Articles
- -Dr. Chatha originally forwarded this paper on Cell Processor
- CODES+ISSS 2007 Tutorial summary on Cell Processor
- Kahle, J., The Cell Processor Architecture, IBM, MICRO-38. 38th Annual IEEE/ACM International Symposium on Microarchitecture, 12-16 Nov. 2005
- M. Day, P. Hofstee, Hardware and software architectures for the CELL processor, IBM Systems&Technology Group, Austin, TX, Hardware/Software Codesign and System Synthesis, CODES+ISSS, Sept. 2005
- D. Stasiak, R. Chaudhry, D. Cox, S. Posluszny, J. Warnock, S. Weitzel, D. Wendel, M. Wang, Cell processor low-power design methodology Syst. & Technol. Group, IBM Corp., Austin, TX, USA, Micro, IEEE, Volume: 25 , Issue: 6 pp. 71-78, Nov.-Dec. 2005
- S. Maeda, S. Asano, T. Shimada, K. Awazu, H. Tago, A real-time software platform for the Cell processor, Toshiba Corp., Japan, Micro, IEEE, Volume: 25 , Issue: 5, pp. 20-29, Sept.-Oct. 2005
