Difference between revisions of "EEE525 VLSI Design"
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| + | == Project == | ||
| + | *[http://www.nanohub.org/resource_files/2007/05/02700/2007.04.25-koh-nt501.pdf Metal Capacitance, 20fF/um ??] | ||
| + | |||
| + | == Digital Design == | ||
| + | *[http://books.google.com/books?id=xEYhxhs7fDgC&pg=PA107&lpg=PA107&dq=calculate+vih+vil&source=web&ots=6HN_n6MTrA&sig=LZ_ecT-5_2gJGAgYacpGCHQ-vTo&hl=en#PPA99,M1 ''Cmos Logic Circuit Design''] By John P. Uyemura (Google online) | ||
| + | :-3.1.1 (p.106) Thorough treatment of Inverter VTC, calculating VIL and VIH | ||
| + | |||
| + | === Homework 2 === | ||
| + | *prob. 2. [http://6004.csail.mit.edu/currentsemester/ Tutorial problems with answers from MIT] | ||
| + | *prob. 2. [http://inst.eecs.berkeley.edu/~ee105/fa98/lectures_fall_98/093098_lecture16.pdf Voltage Transfer Characteristics from Berkeley] | ||
| + | |||
| + | === Homework 3 === | ||
| + | *[http://www.enel.ucalgary.ca/~laleh/courses/encm467/CadenceLayoutTips.pdf parasitic probe?] | ||
| + | *[http://ocw.mit.edu/NR/rdonlyres/Electrical-Engineering-and-Computer-Science/6-012Fall-2005/9414AB80-74F9-4FD9-9E61-5B62EBEB74C2/0/cadence_tutrial2.pdf Tutorial from MIT], calculating avg/integral | ||
| + | |||
| + | ==== More Cadence Tutorials ==== | ||
| + | *[http://www.ece.umd.edu/class/enee359a.S2007/p4.pdf Cadence Tools Tutorial from beginning to automatically generated counter layout] | ||
| + | *[http://www.iaik.tugraz.at/teaching/05_vlsi-design/manual/cadence_fc/index.php Full-Custom Design with Cadence - Tutorial], Graz | ||
| + | |||
== Cadence == | == Cadence == | ||
*[http://www.fulton.asu.edu/ets/services/services/server/unix/Cadence.php Cadence setup on Server] | *[http://www.fulton.asu.edu/ets/services/services/server/unix/Cadence.php Cadence setup on Server] | ||
| + | :Configuration path: <code>/usr/local/cadence2/NCSU </code> | ||
*[http://www.fulton.asu.edu/ets/services/services/server/unix/VLSI.php vlsi2.eas.asu.edu information] | *[http://www.fulton.asu.edu/ets/services/services/server/unix/VLSI.php vlsi2.eas.asu.edu information] | ||
*[http://www.eas.asu.edu/ets/services/services/server/unix/documents/vlsi10.pdf VLSI Readme], with Cadence instructions | *[http://www.eas.asu.edu/ets/services/services/server/unix/documents/vlsi10.pdf VLSI Readme], with Cadence instructions | ||
| + | *> [http://www.esoterum.org/mw/images/7/70/Vlsi2.eas.asu.edu-readme.pdf vlsi2 Read-me file] | ||
| + | |||
| + | === Virtuoso === | ||
| + | *[http://bwrc.eecs.berkeley.edu/Classes/Icdesign/ee141_f03/CadenceLabs/Lab2/VirtuosoTutorial.htm Layout tutorial from Berkeley] | ||
| + | *To add labels and pin names etc., use the Res, Cap or Diode name layer. | ||
| + | *[http://www.es.lth.se/home/jpr/myguide/Personal.html On the "cannot be found in the switched master of the instance" ERROR] | ||
| + | |||
| + | === Tutorials === | ||
| + | *>> [http://ocw.mit.edu/NR/rdonlyres/Electrical-Engineering-and-Computer-Science/6-012Fall-2005/9414AB80-74F9-4FD9-9E61-5B62EBEB74C2/0/cadence_tutrial2.pdf Advanced calculator tutorial from MIT] | ||
| + | *> [http://www.ee.ucla.edu/~dejan/ee115c/ee115c_tut_5.htm Advanced tutorial from UCLA] | ||
| + | *> [http://ece.uwaterloo.ca/~ece438/projects/CadenceTut.pdf UWaterloo Tutorial], thorough on parametric analysis with some pPar information | ||
| + | *> [http://www.seas.upenn.edu/~ese570/manual_14.htm Tutorial at UPenn] | ||
| + | *> [http://www.seas.upenn.edu/~ese570/ESE570_Lab2.pdf Lab Tutorial at UPenn] | ||
| + | *> [http://www.vlsi.wpi.edu/cds/ Tutorial at WPI] | ||
| + | *> [http://www-scf.usc.edu/~ee577/cadence_tutorial4.html Tutorial at USC], Ppar variable information | ||
| + | *> [http://www.ece.nmsu.edu/vlsi/cadence/CADENCE%20Manual.pdf Cadence Manual at NMSU] | ||
| + | *[http://www.eas.asu.edu/~cadence/setup.html Tutorial, VLSI] | ||
| + | *[http://www.ece.osu.edu/~bibyk/ee721/comptut.pdf Tutorial on Virtuoso Schematic editor from OSU], layout with ALU | ||
| + | *[http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_s04/CadenceLabs/Lab2/VirtuosoTutorial.htm Berkeley Virtuoso tutorial] | ||
| + | *[http://trinity.senecac.on.ca/ Cadence FAQ] | ||
| + | *[http://www.tec.ufl.edu/~isj/verification.html#novddorgnd NCSU CDK User FAQ] | ||
| + | *[http://www.utdallas.edu/~liuhao/paper/Circuit%20Simulation%20using%20Spectre.pdf Circuit simulation using Spectre] (UT Dallas) | ||
| + | *[http://www.ece.nmsu.edu/vlsi/cadence/CAD_tips_V1.pdf Unlocking files] | ||
| + | :-At the shell prompt, type <code>clsAdminTool</code>, you'll get a <code>></code> prompt. | ||
| + | :-Type <code>ale /afs/asu.edu/users/m/b/a/mbaker7/cadence/EE525</code> (using the correct path to your library). You should get a list of existing locks in that library. | ||
| + | :-There are two ways to release the lock in question: | ||
| + | ::To release all the locks in the library, type <code>are /full/path/to/your/library/directory</code> | ||
| + | ::To release the lock on a particular file, type <code>asre /full/path/to/the/locked/file</code> | ||
| + | :-Type <code>quit</code> or <code>exit</code>. | ||
| + | |||
| + | === Spectre === | ||
| + | *[http://www.ece.uci.edu/eceware/cadence/spectreuser/spectreuserIX.html Spectre documentation from UCI.edu] | ||
| + | |||
| + | === Design Rules === | ||
| + | *[http://www.mosis.com/Technical/Designrules/scmos/scmos-main.html#tech-codes Mosis design rules] ([http://www.mosis.com/Technical/Layermaps/lm-scmos_scn5m.html SCN5M Deep]) | ||
| + | |||
| + | === Spectre === | ||
| + | *Model Libraries: | ||
| + | <code> | ||
| + | :/usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dN.m | ||
| + | :/usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dP.m | ||
| + | </code> | ||
Latest revision as of 05:13, 24 April 2008
Contents
Project
Digital Design
- Cmos Logic Circuit Design By John P. Uyemura (Google online)
- -3.1.1 (p.106) Thorough treatment of Inverter VTC, calculating VIL and VIH
Homework 2
- prob. 2. Tutorial problems with answers from MIT
- prob. 2. Voltage Transfer Characteristics from Berkeley
Homework 3
- parasitic probe?
- Tutorial from MIT, calculating avg/integral
More Cadence Tutorials
- Cadence Tools Tutorial from beginning to automatically generated counter layout
- Full-Custom Design with Cadence - Tutorial, Graz
Cadence
- Configuration path:
/usr/local/cadence2/NCSU
- vlsi2.eas.asu.edu information
- VLSI Readme, with Cadence instructions
- > vlsi2 Read-me file
Virtuoso
- Layout tutorial from Berkeley
- To add labels and pin names etc., use the Res, Cap or Diode name layer.
- On the "cannot be found in the switched master of the instance" ERROR
Tutorials
- >> Advanced calculator tutorial from MIT
- > Advanced tutorial from UCLA
- > UWaterloo Tutorial, thorough on parametric analysis with some pPar information
- > Tutorial at UPenn
- > Lab Tutorial at UPenn
- > Tutorial at WPI
- > Tutorial at USC, Ppar variable information
- > Cadence Manual at NMSU
- Tutorial, VLSI
- Tutorial on Virtuoso Schematic editor from OSU, layout with ALU
- Berkeley Virtuoso tutorial
- Cadence FAQ
- NCSU CDK User FAQ
- Circuit simulation using Spectre (UT Dallas)
- Unlocking files
- -At the shell prompt, type
clsAdminTool, you'll get a>prompt. - -Type
ale /afs/asu.edu/users/m/b/a/mbaker7/cadence/EE525(using the correct path to your library). You should get a list of existing locks in that library. - -There are two ways to release the lock in question:
- To release all the locks in the library, type
are /full/path/to/your/library/directory - To release the lock on a particular file, type
asre /full/path/to/the/locked/file
- To release all the locks in the library, type
- -Type
quitorexit.
Spectre
Design Rules
Spectre
- Model Libraries:
- /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dN.m
- /usr/local/cadence/NCSU/local/models/spectre/standalone/tsmc25dP.m
