|
|
| | + | == Project == |
| | + | *[http://www.nanohub.org/resource_files/2007/05/02700/2007.04.25-koh-nt501.pdf Metal Capacitance, 20fF/um ??] |
| | + | |
| | + | == Digital Design == |
| | + | *[http://books.google.com/books?id=xEYhxhs7fDgC&pg=PA107&lpg=PA107&dq=calculate+vih+vil&source=web&ots=6HN_n6MTrA&sig=LZ_ecT-5_2gJGAgYacpGCHQ-vTo&hl=en#PPA99,M1 ''Cmos Logic Circuit Design''] By John P. Uyemura (Google online) |
| | + | :-3.1.1 (p.106) Thorough treatment of Inverter VTC, calculating VIL and VIH |
| | + | |
| | + | === Homework 2 === |
| | + | *prob. 2. [http://6004.csail.mit.edu/currentsemester/ Tutorial problems with answers from MIT] |
| | + | *prob. 2. [http://inst.eecs.berkeley.edu/~ee105/fa98/lectures_fall_98/093098_lecture16.pdf Voltage Transfer Characteristics from Berkeley] |
| | + | |
| | + | === Homework 3 === |
| | + | *[http://www.enel.ucalgary.ca/~laleh/courses/encm467/CadenceLayoutTips.pdf parasitic probe?] |
| | + | *[http://ocw.mit.edu/NR/rdonlyres/Electrical-Engineering-and-Computer-Science/6-012Fall-2005/9414AB80-74F9-4FD9-9E61-5B62EBEB74C2/0/cadence_tutrial2.pdf Tutorial from MIT], calculating avg/integral |
| | + | |
| | + | ==== More Cadence Tutorials ==== |
| | + | *[http://www.ece.umd.edu/class/enee359a.S2007/p4.pdf Cadence Tools Tutorial from beginning to automatically generated counter layout] |
| | + | *[http://www.iaik.tugraz.at/teaching/05_vlsi-design/manual/cadence_fc/index.php Full-Custom Design with Cadence - Tutorial], Graz |
| | + | |
| | == Cadence == | | == Cadence == |
Exception encountered, of type "Error"